LSI logic testing — An overview

DOI10.1109/TC.1981.6312152MaRDI QIDQ3904528zbMATH OpenOpenAlexFDO

Authors Eugen I. Muehldorf, Anil D. Savkar

Publication date 1981

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1981.6312152

zbMATH Keywords

Boolean differencefault modelingfault simulationlarge scale integrationpath sensitizationtest pattern generation

Mathematics Subject Classification ID

Research exposition (monographs, survey articles) pertaining to information and communication theory (94-02)

Cited in

(4)

• Functional test generation using binary decision diagrams
• Efficient VLSI fault simulation
• A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits
• Graph partitioning applied to the logic testing of combinational circuits

This page was built for publication: LSI logic testing — An overview

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3904528)