Mapping uniform loop nests onto distributed memory architectures

DOI10.1016/0167-8191(94)90001-9MaRDI QIDQ1323636zbMATH OpenOpenAlexFDO

Authors Alain Darte, Yves Robert

Publication date 1 June 1994

Published in Parallel Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-8191(94)90001-9

zbMATH Keywords

mappingschedulingpartitioningautomatic parallelizationloop transformationsdistributed-memory machinesarray alignmentuniform loop nests

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

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(14)

• A consistent generation of pipeline parallelism and distribution of operations and data among processors
• Geometrical tools to map systems of affine recurrence equations on regular arrays
• Optimal data scheduling for uniform multidimensional applications
• A computation + communication load balanced loop partitioning method for distributed memory systems
• Resource-constrained scheduling of partitioned algorithms on processor arrays
• Three mapping loop strategies for the upper diagonal matrix-vector product
• Mapping of affine loop nests onto independent processors
• A reindexing based approach towards mapping of DAG with affine schedules onto parallel embedded systems
• Semi-automatic composition of loop transformations for deep parallelism and memory hierarchies
• Some efficient solutions to the affine scheduling problem. I: One- dimensional time
• Refinement based techniques for mapping nested loop algorithms onto linear systolic arrays
• The local memory access sequence of multiple induction variables on distributed memory machines
• Mapping loop nests to multipipelined architecture
• Partitioning and mapping nested loops on multicomputers

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