Refinement based techniques for mapping nested loop algorithms onto linear systolic arrays
From MaRDI portal
Publication:3136231
Recommendations
- Synthesizing linear array algorithms from nested FOR loop algorithms
- Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
- EFFICIENT MAPPING REDUCTIONS USING ISO-PLANES ON THE POLYTOPE MODEL
- Mapping uniform loop nests onto distributed memory architectures
- A methodology for algorithm regularization and mapping into time-optimal VLSI arrays
Cited in
(3)
This page was built for publication: Refinement based techniques for mapping nested loop algorithms onto linear systolic arrays
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3136231)