Memory power reduction for high-speed implementation of turbo codes

DOI10.1023/A:1022132031284MaRDI QIDQ1405497zbMATH OpenOpenAlexFDO

Authors F. Maessen, A. Giulietti, Bruno Bougard, Liesbet van der Perre, Veerle Derudder, Francky Catthoor

Publication date 25 August 2003

Published in Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1023/a:1022132031284

zbMATH Keywords

low powerturbo codeslow latencyMAP algorithmmemory optimization

Mathematics Subject Classification ID

Coding and information theory (compaction, compression, models of communication, encoding schemes, etc.) (aspects in computer science) (68P30)

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(4)

• A scalable system architecture for high-throughput turbo-decoders
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• Reconfigurable turbo decoding for 3G applications
• Memory-reduced maximum a posteriori probability decoding for high-throughput parallel turbo decoders

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