Multiplexer-based array multipliers

DOI10.1109/12.743408MaRDI QIDQ4571388zbMATH OpenOpenAlexFDO

Authors K. Z. Pekmestzi

Publication date 9 July 2018

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.743408

Mathematics Subject Classification ID

Numerical algorithms for computer arithmetic, etc. (65Y04) Mathematical problems of computer architecture (68M07) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cited in

(6)

• Low-complexity multiplexer-based normal basis multiplier over GF(2ᵐ)
• Multiplexer implementation of low-complexity polynomial basis multiplier in \(\mathrm{GF}(2^m)\) using all one polynomial
• Novel bit-parallel multiplier for \(\mathrm{GF}(2^m)\) defined by all-one polynomial using generalized Karatsuba algorithm
• Operand Folding Hardware Multipliers
• scientific article; zbMATH DE number 3890726 (Why is no real title available?)
• An algorithm for assigning multiplexer inputs

This page was built for publication: Multiplexer-based array multipliers

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4571388)