On model checking synchronised hardware circuits

DOI10.1007/3-540-44464-5_14MaRDI QIDQ2766537zbMATH OpenFDO

Authors Martin Leucker

Publication date 28 January 2002

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/3-540-44464-5_14

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

Recommendations

• Automatic verification methods for finite state systems. International workshop, Grenoble, France, June 12-14, 1989. Proceedings
• Automatic verification of finite-state concurrent systems using temporal logic specifications
• Symbolic model checking: \(10^{20}\) states and beyond
• Automatic Verification of Sequential Circuits Using Temporal Logic
• Sequential and distributed model checking of Petri net specifications

Cited in

(2)

• Model checking: a hardware design perspective
• scientific article; zbMATH DE number 5967673 (Why is no real title available?)

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Uses Software

• LUSTRE

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