Optimal circuits for parallel multipliers

DOI10.1109/12.660163MaRDI QIDQ4571452zbMATH OpenOpenAlexFDO

Authors Paul Stelling, Vojin G. Oklobdzija, R. Ravi, Chip Martel

Publication date 9 July 2018

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.660163

Mathematics Subject Classification ID

Numerical algorithms for computer arithmetic, etc. (65Y04) Mathematical problems of computer architecture (68M07) Analytic circuit theory (94C05)

Cited in

(6)

• Shallow circuits and concise formulae for multiple addition and multiplication
• Computer arithmetic and hardware: ``off the shelf microprocessors versus ``custom hardware
• Circuit level realization of low latency radix-4 Booth scheme for parallel multipliers
• scientific article; zbMATH DE number 1307000 (Why is no real title available?)
• scientific article; zbMATH DE number 1950621 (Why is no real title available?)
• Novel designs of nanometric parity preserving reversible compressor

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