Partitioned Matrix Algorithms for VLSI Arithmetic Systems

DOI10.1109/TC.1982.1675945MaRDI QIDQ3960038zbMATH OpenOpenAlexFDO

Authors Kai Hwang, Yeng-Heng Cheng

Publication date 1982

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1982.1675945

zbMATH Keywords

computer architecturecomputer arithmeticinversionlarge-scale matrix solverslinear system of equationsLU decompositionmatrix computationsnumerical analysisparallel processingreal-time applicationstriangular matrixvery large scale integration

Mathematics Subject Classification ID

Software, source code, etc. for problems pertaining to numerical analysis (65-04) Direct numerical methods for linear systems and matrix inversion (65F05) Theory of operating systems (68N25) Circuits, networks (94C99)

Cited in

(6)

• Mapping dynamic programming onto modular linear systolic arrays
• Calculating an inverse matrix for lower triangular matrix using a two-processor system
• A modular systolic linear array for gaussian elimination
• MODULAR FIXED-SIZE VLSI ARCHITECTURES FOR GENERAL MULTISPLITTING ITERATION
• On high-speed computing with a programmable linear array
• Optimal piecewise linear schedules for LSGP- and LPGS-decomposed array processors via quadratic programming

This page was built for publication: Partitioned Matrix Algorithms for VLSI Arithmetic Systems

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3960038)