Partitioning and scheduling DSP applications with maximal memory access hiding

DOI10.1155/S1110865702205041MaRDI QIDQ1773585zbMATH OpenOpenAlexFDO

Authors Zhong Wang, Edwin H.-M. Sha, Yuke Wang

Publication date 3 May 2005

Published in EURASIP Journal on Applied Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1155/s1110865702205041

zbMATH Keywords

iteration space partitioning scheme

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Signal theory (characterization, reconstruction, filtering, etc.) (94A12)

Review text

Summary: This paper presents an iteration space partitioning scheme to reduce the CPU idle time due to the long memory access latency. We take into consideration both the data accesses of intermediate and initial data. An algorithm is proposed to find the largest overlap for initial data to reduce the entire memory traffic. In order to efficiently hide the memory latency, another algorithm is developed to balance the ALU and memory schedules. The experiments on DSP benchmarks show that the algorithms significantly outperform the known existing methods.

Recommendations

• Minimizing average schedule length under memory constraints by optimal partitioning and prefetching
• Partitioning processor arrays under resource constraints
• A MEMETIC ALGORITHM FOR PERFORMING MEMORY ASSIGNMENT IN DUAL-BANK DSPS
• scientific article; zbMATH DE number 2242709
• Optimal data scheduling for uniform multidimensional applications

Cited in

(2)

• Power-Aware Variable Partitioning for DSPs With Hybrid PRAM and DRAM Main Memory
• Minimizing average schedule length under memory constraints by optimal partitioning and prefetching

This page was built for publication: Partitioning and scheduling DSP applications with maximal memory access hiding

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1773585)