| Publication | Date of Publication | Type |
|---|
Testable MUTEX Design
IEEE Transactions on Circuits and Systems I: Regular Papers | 2021-08-26 | Paper |
Self-diagnosis of regular arrays of processors
Computers and Electrical Engineering | 1993-04-01 | Paper |
Test schedules for VLSI circuits having built-in test hardware
Computers & Mathematics with Applications | 1987-01-01 | Paper |
Incremental Processing Applied to Munkres’ Algorithm and Its Application in Steinberg’s Placement Procedure
SIAM Journal on Algebraic Discrete Methods | 1985-01-01 | Paper |
An optimum testing algorithm for some symmetric coherent systems
Journal of Mathematical Analysis and Applications | 1984-01-01 | Paper |
Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect–Cause Analysis
IEEE Transactions on Computers | 1982-01-01 | Paper |
Probabilistic Aspects of Boolean Switching Functions via a New Transform
Journal of the ACM | 1981-01-01 | Paper |
A Fault-Collapsing Analysis in Sequential Logic Networks
Bell System Technical Journal | 1981-01-01 | Paper |
Functional Level Primitives in Test Generation
IEEE Transactions on Computers | 1980-01-01 | Paper |
A probabilistic model for the analysis of the routing process for circuits
Networks | 1980-01-01 | Paper |
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers | 1980-01-01 | Paper |
A forced directed component placement procedure for printed circuit boards
IEEE Transactions on Circuits and Systems | 1979-01-01 | Paper |
On Redundancy and Fault Detection in Sequential Circuits
IEEE Transactions on Computers | 1979-01-01 | Paper |
| scientific article; zbMATH DE number 3590198 (Why is no real title available?) | 1977-01-01 | Paper |
Identification of Multiple Stuck-Type Faults in Combinational Networks
IEEE Transactions on Computers | 1976-01-01 | Paper |
Procedures for Eliminating Static and Dynamic Hazards in Test Generation
IEEE Transactions on Computers | 1974-01-01 | Paper |
The Effects of Races, Delays, and Delay Faults on Test Generation
IEEE Transactions on Computers | 1974-01-01 | Paper |
A Note on Three-Valued Logic Simulation
IEEE Transactions on Computers | 1972-01-01 | Paper |
Generation of Fault Tests for Linear Logic Networks
IEEE Transactions on Computers | 1972-01-01 | Paper |
A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits
IEEE Transactions on Computers | 1971-01-01 | Paper |
Simplification of the Covering Problem with Application to Boolean Expressions
Journal of the ACM | 1970-01-01 | Paper |
Functional Partitioning and Simulation of Digital Circuits
IEEE Transactions on Computers | 1970-01-01 | Paper |
Generation of optimal code for expressions via factorization
Communications of the ACM | 1969-01-01 | Paper |
Combinatorial equivalence of (0,1) circulant matrices
Journal of Computer and System Sciences | 1969-01-01 | Paper |
An unexpected result in coding the vertices of a graph
Journal of Mathematical Analysis and Applications | 1967-01-01 | Paper |
Adaptive computers
Information and Control | 1967-01-01 | Paper |
Coding the vertexes of a graph
IEEE Transactions on Information Theory | 1966-01-01 | Paper |
Implementation of Threshold Nets by Integer Linear Programming
IEEE Transactions on Electronic Computers | 1965-01-01 | Paper |
Techniques for the simulation of computer logic
Communications of the ACM | 1964-01-01 | Paper |
The Borel-Tanner distribution
Biometrika | 1960-01-01 | Paper |
