Hsie-Chia Chang

Available identifiers

zbMath Open chang.hsie-chiaMaRDI QIDQ2732729

List of research outcomes

Publication	Date of Publication	Type
High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver	2021-08-26	Paper
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture	2021-08-26	Paper
Self-Compensation Technique for Simplified Belief-Propagation Algorithm	2018-06-12	Paper
Design of a power-reduction Viterbi decoder for WLAN applications	2017-11-20	Paper
Turbo decoder architecture for beyond-4G applications	2013-08-21	Paper
An efficient countermeasure against correlation power-analysis attacks with randomized Montgomery operations for DF-ECC processor	2012-11-13	Paper
New serial architecture for the Berlekamp-Massey algorithm	2001-09-04	Paper

Research outcomes over time

This page was built for person: Hsie-Chia Chang