Massimo Alioto

Available identifiers

Publication	Date of Publication	Type
Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read	2021-09-02	Paper
Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits	2021-08-26	Paper
Variations in Nanometer CMOS Flip-Flops: Part II—Energy Variability and Impact of Other Sources of Variations	2021-08-26	Paper
Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing	2021-08-26	Paper
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial	2021-08-26	Paper
A feedback strategy to improve the entropy of a chaos-based random bit generator	2017-11-20	Paper
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map	2017-11-20	Paper
Modeling and Evaluation of Positive-Feedback Source-Coupled Logic	2017-10-04	Paper
A simple strategy for optimized design of one-level carry-skip adders	2017-08-25	Paper
Simple and accurate modeling of the output transition time in nanometer CMOS gates	2011-02-17	Paper
Modelling and design considerations on CML gates under high-current effects	2006-02-21	Paper
Power-delay optimization of D-latch/MUX source coupled logic gates	2005-03-08	Paper
An efficient implementation of PRNGs based on the digital sawtooth map	2005-01-12	Paper
Modelling of source-coupled logic gates	2002-09-25	Paper

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