Modelling of source-coupled logic gates

DOI10.1002/CTA.188zbMath1010.94563OpenAlexW1963523193WikidataQ57846325 ScholiaQ57846325MaRDI QIDQ3149541

Salvatore Pennisi, Massimo Alioto, Gaetano Palumbo

Publication date: 25 September 2002

Published in: International Journal of Circuit Theory and Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1002/cta.188

zbMATH Keywords

modellingpropagation delaynoise margincurrent mode logic gatesSCL gatessource-coupled logic gates

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

Related Items (1)

Power-delay optimization of D-latch/MUX source coupled logic gates

This page was built for publication: Modelling of source-coupled logic gates