Power-delay optimization of D-latch/MUX source coupled logic gates
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Publication:4655741
DOI10.1002/CTA.305zbMath1061.94549OpenAlexW2014694497MaRDI QIDQ4655741
Massimo Alioto, Gaetano Palumbo
Publication date: 8 March 2005
Published in: International Journal of Circuit Theory and Applications (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1002/cta.305
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