Power-delay optimization of D-latch/MUX source coupled logic gates

DOI10.1002/CTA.305MaRDI QIDQ4655741zbMATH OpenOpenAlexFDO

Authors Massimo Alioto, G. Palumbo

Publication date 8 March 2005

Published in International Journal of Circuit Theory and Applications (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1002/cta.305

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

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Cites work

• Modelling of source-coupled logic gates

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(3)

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