Power-delay optimization of D-latch/MUX source coupled logic gates (Q4655741)

From MaRDI portal
scientific article; zbMATH DE number 2142497
Language Label Description Also known as
English
Power-delay optimization of D-latch/MUX source coupled logic gates
scientific article; zbMATH DE number 2142497

    Statements

    Power-delay optimization of D-latch/MUX source coupled logic gates (English)
    0 references
    0 references
    0 references
    8 March 2005
    0 references

    Identifiers