Power-delay optimization of D-latch/MUX source coupled logic gates (Q4655741)
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scientific article; zbMATH DE number 2142497
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| English | Power-delay optimization of D-latch/MUX source coupled logic gates |
scientific article; zbMATH DE number 2142497 |
Statements
Power-delay optimization of D-latch/MUX source coupled logic gates (English)
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8 March 2005
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0.7867295145988464
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0.677362322807312
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0.6605798006057739
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