Jacob Savir

List of research outcomes

This list is not complete and representing at the moment only items from zbMATH Open and arXiv. We are working on additional sources - please check back here soon!

Publication	Date of Publication	Type
Random pattern testability of memory control logic IEEE Transactions on Computers	2018-07-09	Paper
Reducing the MISR size IEEE Transactions on Computers	1996-01-01	Paper
Fault Propagation Through Embedded Multiport Memories IEEE Transactions on Computers	1987-01-01	Paper
Random Pattern Testability IEEE Transactions on Computers	1984-01-01	Paper
On Random Pattern Test Length IEEE Transactions on Computers	1984-01-01	Paper
A New Empirical Test for the Quality of Random Integer Generators IEEE Transactions on Computers	1983-01-01	Paper
The Weighted Syndrome Sums Approach to VLSI Testing IEEE Transactions on Computers	1981-01-01	Paper
Syndrome-Testable Design of Combinational Circuits IEEE Transactions on Computers	1980-01-01	Paper
Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection IEEE Transactions on Computers	1980-01-01	Paper
Detection of Single Intermittent Faults in Sequential Circuits IEEE Transactions on Computers	1980-01-01	Paper
Correction to "Syndrome-Testable Design of Combinational Circuits" IEEE Transactions on Computers	1980-01-01	Paper

Research outcomes over time

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