Stefano Tonetta

Available identifiers

zbMath Open tonetta.stefanoMaRDI QIDQ479825

List of research outcomes

Publication	Date of Publication	Type
Extended bounded response LTL: a new safety fragment for efficient reactive synthesis	2025-01-13	Paper
Expressiveness of extended bounded response \textsf{LTL}	2024-12-06	Paper
A first-order logic characterisation of safety and co-safety languages	2024-01-23	Paper
Searching for ribbon-shaped paths in fair transition systems	2024-01-23	Paper
Verification Modulo theories	2023-10-30	Paper
A first-order logic characterization of safety and co-safety languages	2023-08-26	Paper
Fairness, assumptions, and guarantees for extended bounded response \textsf{LTL+P} synthesis	2023-05-26	Paper
Assumption-based runtime verification	2023-05-08	Paper
\(\mathsf{GR}(1)\) is equivalent to \(\mathsf{R}(1)\)	2022-10-28	Paper
Safe Decomposition of Startup Requirements: Verification and Synthesis	2022-10-13	Paper
Diagnosability of fair transition systems	2022-07-08	Paper
Implicit semi-algebraic abstraction for polynomial dynamical systems	2022-03-25	Paper
https://portal.mardi4nfdi.de/entity/Q3384172	2021-12-14	Paper
Certifying proofs for SAT-based model checking	2021-12-08	Paper
Formal specification and verification of dynamic parametrized architectures	2021-05-04	Paper
SMT-based satisfiability of first-order LTL with event freezing functions and metric operators	2020-05-26	Paper
Infinite-State Liveness-to-Safety via Implicit Abstraction and Well-Founded Relations	2019-05-03	Paper
Tightening the contract refinements of a system architecture	2018-08-08	Paper
Infinite-state invariant checking with IC3 and predicate abstraction	2017-07-26	Paper
Formal Safety Assessment via Contract-Based Design	2015-12-17	Paper
HRELTL: a temporal logic for hybrid systems	2015-12-07	Paper
Formal Design of Asynchronous Fault Detection and Identification Components using Temporal Epistemic Logic	2015-11-05	Paper
Quantifier-free encoding of invariants for hybrid systems	2014-12-05	Paper
Loop summarization using state and transition invariants	2014-06-30	Paper
SMT-based scenario verification for hybrid systems	2014-03-28	Paper
From Sequential Extended Regular Expressions to NFA with Symbolic Labels	2011-02-11	Paper
Correct Hardware Design and Verification Methods	2010-02-05	Paper
Requirements Validation for Hybrid Systems	2009-06-30	Paper
Loop Summarization Using Abstract Transformers	2008-11-20	Paper
Boolean Abstraction for Temporal Logic Satisfiability	2007-11-29	Paper
GSTE is partitioned model checking	2007-10-11	Paper
Property-Driven Partitioning for Abstraction Refinement	2007-09-03	Paper
Computer Aided Verification	2006-01-10	Paper
Computer Aided Verification	2005-08-25	Paper

Research outcomes over time

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