| Publication | Date of Publication | Type |
|---|
Extended bounded response LTL: a new safety fragment for efficient reactive synthesis
Formal Methods in System Design | 2025-01-13 | Paper |
Expressiveness of extended bounded response \textsf{LTL}
| 2024-12-06 | Paper |
A first-order logic characterisation of safety and co-safety languages
Lecture Notes in Computer Science | 2024-01-23 | Paper |
Searching for ribbon-shaped paths in fair transition systems
| 2024-01-23 | Paper |
Verification Modulo theories
Formal Methods in System Design | 2023-10-30 | Paper |
A first-order logic characterization of safety and co-safety languages
Logical Methods in Computer Science | 2023-08-26 | Paper |
Fairness, assumptions, and guarantees for extended bounded response \textsf{LTL+P} synthesis
Software Engineering and Formal Methods | 2023-05-26 | Paper |
Assumption-based runtime verification
Formal Methods in System Design | 2023-05-08 | Paper |
\(\mathsf{GR}(1)\) is equivalent to \(\mathsf{R}(1)\)
Information Processing Letters | 2022-10-28 | Paper |
Safe decomposition of startup requirements: verification and synthesis
Tools and Algorithms for the Construction and Analysis of Systems | 2022-10-13 | Paper |
Diagnosability of fair transition systems
Artificial Intelligence | 2022-07-08 | Paper |
Implicit semi-algebraic abstraction for polynomial dynamical systems
| 2022-03-25 | Paper |
Linear-time temporal logic with event freezing functions
| 2021-12-14 | Paper |
Certifying proofs for SAT-based model checking
Formal Methods in System Design | 2021-12-08 | Paper |
Formal specification and verification of dynamic parametrized architectures
| 2021-05-04 | Paper |
SMT-based satisfiability of first-order LTL with event freezing functions and metric operators
Information and Computation | 2020-05-26 | Paper |
Infinite-state liveness-to-safety via implicit abstraction and well-founded relations
Computer Aided Verification | 2019-05-03 | Paper |
Tightening the contract refinements of a system architecture
Formal Methods in System Design | 2018-08-08 | Paper |
Infinite-state invariant checking with IC3 and predicate abstraction
Formal Methods in System Design | 2017-07-26 | Paper |
Formal safety assessment via contract-based design
Automated Technology for Verification and Analysis | 2015-12-17 | Paper |
HRELTL: a temporal logic for hybrid systems
Information and Computation | 2015-12-07 | Paper |
Formal Design of Asynchronous Fault Detection and Identification Components using Temporal Epistemic Logic
Logical Methods in Computer Science | 2015-11-05 | Paper |
Quantifier-free encoding of invariants for hybrid systems
Formal Methods in System Design | 2014-12-05 | Paper |
Loop summarization using state and transition invariants
Formal Methods in System Design | 2014-06-30 | Paper |
SMT-based scenario verification for hybrid systems
Formal Methods in System Design | 2014-03-28 | Paper |
From sequential extended regular expressions to NFA with symbolic labels
Implementation and Application of Automata | 2011-02-11 | Paper |
``More deterministic vs. ``smaller Büchi automata for efficient LTL model checking
Lecture Notes in Computer Science | 2010-02-05 | Paper |
Requirements Validation for Hybrid Systems
Computer Aided Verification | 2009-06-30 | Paper |
Loop Summarization Using Abstract Transformers
Automated Technology for Verification and Analysis | 2008-11-20 | Paper |
Boolean Abstraction for Temporal Logic Satisfiability
Computer Aided Verification | 2007-11-29 | Paper |
GSTE is partitioned model checking
Formal Methods in System Design | 2007-10-11 | Paper |
Property-Driven Partitioning for Abstraction Refinement
Tools and Algorithms for the Construction and Analysis of Systems | 2007-09-03 | Paper |
Computer Aided Verification
Lecture Notes in Computer Science | 2006-01-10 | Paper |
Computer Aided Verification
Lecture Notes in Computer Science | 2005-08-25 | Paper |
