Correct Hardware Design and Verification Methods
From MaRDI portal
Publication:5897061
DOI10.1007/b93958zbMath1179.68095OpenAlexW219731125MaRDI QIDQ5897061
Roberto Sebastiani, Stefano Tonetta
Publication date: 5 February 2010
Published in: Lecture Notes in Computer Science (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/b93958
Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60)
Related Items (10)
Graph Games and Reactive Synthesis ⋮ GSTE is partitioned model checking ⋮ Experiments with deterministic \(\omega\)-automata for formulas of linear temporal logic ⋮ Finding and fixing faults ⋮ Mechanizing the Powerset Construction for Restricted Classes of ω-Automata ⋮ Linear temporal logic symbolic model checking ⋮ From LTL and Limit-Deterministic Büchi Automata to Deterministic Parity Automata ⋮ GOAL Extended: Towards a Research Tool for Omega Automata and Temporal Logic ⋮ Tool support for learning Büchi automata and linear temporal logic ⋮ On the Relationship between LTL Normal Forms and Büchi Automata
Uses Software
This page was built for publication: Correct Hardware Design and Verification Methods