Algorithm partition and parallel recognition of general context-free languages using fixed-size VLSI architecture

DOI10.1016/0031-3203(86)90003-8zbMath0606.68078OpenAlexW2026227831MaRDI QIDQ1084875

B. George

Publication date: 1986

Published in: Pattern Recognition (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0031-3203(86)90003-8

zbMATH Keywords

dynamic programmingcontext-free language recognition

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Formal languages and automata (68Q45) Dynamic programming (90C39) Pattern recognition, speech recognition (68T10) Algorithms in computer science (68W99)

Related Items (3)

Algorithm partition and parallel recognition of general context-free languages using fixed-size VLSI architecture ⋮ VLSI architectures for string matching and pattern matching ⋮ Efficient reconfigurable embedded parsers

Cites Work

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• Algorithm partition and parallel recognition of general context-free languages using fixed-size VLSI architecture
• General context-free recognition in less than cubic time
• Parallel Parsing Algorithms and VLSI Implementations for Syntactic Pattern Recognition
• Speed of Recognition of Context-Free Languages by Array Automata
• A modification of Warshall's algorithm for the transitive closure of binary relations
• A Theorem on Boolean Matrices

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