Functional test generation using binary decision diagrams

DOI10.1016/0898-1221(87)90072-1zbMATH Open0641.94035OpenAlexW1980014718MaRDI QIDQ1101072FDOQ1101072

Authors: H. K. Reghbati, Magdy S. Abadir 

Publication date: 1987

Published in: Computers & Mathematics with Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0898-1221(87)90072-1

zbMATH Keywords

fault detectionbinary decision diagramsintegrated circuitsextension to the D-algorithmLSI/VLSI circuitnetwork of interconnected modules

Mathematics Subject Classification ID

Cites Work

• Binary Decision Diagrams
• Title not available (Why is that?)
• Test Generation for Microprocessors
• Title not available (Why is that?)
• Functional Level Primitives in Test Generation
• LSI logic testing — An overview
• A Module-Level Testing Approach for Combinational Networks

Cited In (1)

• On the size of binary decision diagrams representing Boolean functions

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