Selective I/O scan: A diagnosable design technique for VLSI systems

DOI10.1016/0898-1221(87)90078-2zbMath0641.94037OpenAlexW2066503614MaRDI QIDQ1101076

K. K. Chau, C. R. Kime

Publication date: 1987

Published in: Computers \& Mathematics with Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0898-1221(87)90078-2

zbMATH Keywords

VLSIfault diagnosistest point placement algorithm

Mathematics Subject Classification ID

Cites Work

• An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
• Unnamed Item

This page was built for publication: Selective I/O scan: A diagnosable design technique for VLSI systems