A graph theoretical approach for the yield enhancement of reconfigurable VLSI/WSI arrays

DOI10.1016/S0166-218X(98)00091-2zbMATH Open0913.68020OpenAlexW2004995420MaRDI QIDQ1276972FDOQ1276972

Authors: Jagannathan Narasimhan, Kazuo Nakajima, Chong S. Rim 

Publication date: 2 February 1999

Published in: Discrete Applied Mathematics (Search for Journal in Brave)

Full work available at URL: http://www.elsevier.com/locate/dam

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zbMATH Keywords

pebblescircuit placementcircuit reconfiguration problem

Mathematics Subject Classification ID

Computer system organization (68M99)

Cites Work

• Optimization by simulated annealing
• Title not available (Why is that?)
• Title not available (Why is that?)
• Planar 3DM is NP-complete

Cited In (2)

• Harvest rate of reconfigurable pipelines
• Combining lithography and directed self assembly for the manufacturing of vias: connections to graph coloring problems, integer programming formulations, and numerical experiments

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