A graph theoretical approach for the yield enhancement of reconfigurable VLSI/WSI arrays

DOI10.1016/S0166-218X(98)00091-2MaRDI QIDQ1276972zbMATH OpenOpenAlexFDO

Authors Jagannathan Narasimhan, Kazuo Nakajima, Chong S. Rim

Publication date 2 February 1999

Published in Discrete Applied Mathematics (Search for Journal in Brave)

Full work available at URL http://www.elsevier.com/locate/dam

zbMATH Keywords

pebblescircuit placementcircuit reconfiguration problem

Mathematics Subject Classification ID

Computer system organization (68M99)

Recommendations

• On reconfigurability of VLSI linear arrays
• Publication:4808637
• Publication:3802623
• Testing and reconfiguration of VLSI linear arrays
• A built-in self-repair circuit for restructuring mesh-connected processor arrays by direct spare replacement

Cites work

• scientific article; zbMATH DE number 3639144 (Why is no real title available?)
• scientific article; zbMATH DE number 3793772 (Why is no real title available?)
• Optimization by simulated annealing
• Planar 3DM is NP-complete

Cited in

(2)

• Harvest rate of reconfigurable pipelines
• Combining lithography and directed self assembly for the manufacturing of vias: connections to graph coloring problems, integer programming formulations, and numerical experiments

This page was built for publication: A graph theoretical approach for the yield enhancement of reconfigurable VLSI/WSI arrays

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1276972)