An application of Hopfield networks to worst-case power analysis of RT-level VLSI systems
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Publication:1388293
DOI10.1016/S0020-7225(96)00120-6zbMATH Open0903.68017OpenAlexW2063395897MaRDI QIDQ1388293FDOQ1388293
Authors: Enrico Macii, Massimo Poncino
Publication date: 11 June 1998
Published in: International Journal of Engineering Science (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/s0020-7225(96)00120-6
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