VLSI architecture of modified Euclidean algorithm for Reed-Solomon code.

DOI10.1016/S0020-0255(03)00154-3MaRDI QIDQ1425296zbMATH OpenOpenAlexFDO

Authors D. Massart

Publication date 15 March 2004

Published in Information Sciences (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/s0020-0255(03)00154-3

zbMATH Keywords

Berlekamp's key equationdecoding algorithmError correcting codeEuclidean algorithmReed-Solomon codeVLSI architecture

Mathematics Subject Classification ID

Multiplicative structure; Euclidean algorithm; greatest common divisors (11A05) Reliability, testing and fault tolerance of networks and computer systems (68M15) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Decoding (94B35)

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Cites work

• A design of Reed-Solomon decoder with systolic-array structure
• scientific article; zbMATH DE number 804579 (Why is no real title available?)
• Inversionless decoding of both errors and erasures of Reed-Solomon code
• On decoding of both errors and erasures of a Reed-Solomon code using an inverse-free Berlekamp-Massey algorithm
• Transform Techniques for Error Control Codes

Cited in

(3)

• Recoverability study of SPC product codes under erasure decoding
• Comparison of the VLSI cost/performance properties of two Reed–Solomon decoding algorithms
• scientific article; zbMATH DE number 2219129 (Why is no real title available?)

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