Modular adder designs using optimal reversible and fault tolerant gates in field-coupled QCA nanocomputing

DOI10.1007/S10773-018-3664-ZMaRDI QIDQ1640112zbMATH OpenOpenAlexFDO

Authors Bisma Bilal, Suhaib Ahmed, Vipan Kakkar

Publication date 13 June 2018

Published in International Journal of Theoretical Physics (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s10773-018-3664-z

zbMATH Keywords

adderclockingfault tolerant designnanotechnologyQCAquantum cellsreversible gateuniversal gate

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Cellular automata (computational aspects) (68Q80) Quantum computation (81P68) Quantum dots, waveguides, ratchets, etc. (81Q37) Statistical mechanics of nanostructures and nanoparticles (82D80) Fault detection; testing in circuits and networks (94C12)

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Cites work

• Conservative logic
• scientific article; zbMATH DE number 3692653 (Why is no real title available?)
• Irreversibility and Heat Generation in the Computing Process
• Logical Reversibility of Computation
• Quantum-dot devices and quantum-dot cellular automata.

Cited in

(4)

• Modular design of ultra-efficient reversible full adder-subtractor in QCA with power dissipation analysis
• Design of a fault-tolerant reversible control unit in molecular quantum-dot cellular automata
• Design of quantum dot cellular automata based fault tolerant convolution encoders for secure nanocomputing
• Design for testability of QCA logic under stuck-at-value fault model

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