Design and power analysis of an ultra-high speed fault-tolerant full-adder cell in quantum-dot cellular automata
DOI10.1007/S10773-022-05013-0zbMATH Open1486.81117OpenAlexW4210951951MaRDI QIDQ2113973FDOQ2113973
Authors: Milad Bagherian Khosroshahy, Alireza Abdoli, Amir Masoud Rahmani
Publication date: 14 March 2022
Published in: International Journal of Theoretical Physics (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s10773-022-05013-0
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fault tolerancequantum-dot cellular automataarithmetic computingenergy dissipation analysisfull-adder designsingle-layer circuit design
Quantum computation (81P68) Reliability, testing and fault tolerance of networks and computer systems (68M15) Cellular automata (computational aspects) (68Q80) Network design and communication in computer systems (68M10) Quantum dots, waveguides, ratchets, etc. (81Q37)
Cited In (6)
- Design and evaluation of a carbon nanotube-based programmable architecture
- A novel full adder/subtractor in quantum-dot cellular automata
- Minority Gate Oriented Logic Design with Quantum-Dot Cellular Automata
- A three-layer full adder/subtractor structure in quantum-dot cellular automata
- Design and simulation of modular \(2^n\) to 1 quantum-dot cellular automata (QCA) multiplexers
- Design of a two-bit-per-cell content addressable memory using singe-electron transistors
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