Systematic synthesis of parallel architectures for the computation of higher order cumulants

DOI10.1016/S0167-8191(99)00125-8zbMATH Open0938.68657MaRDI QIDQ1978684FDOQ1978684

Authors: Elias S. Manolakos, Haris M. Stellakis 

Publication date: 4 June 2000

Published in: Parallel Computing (Search for Journal in Brave)

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zbMATH Keywords

parallel processinghigher order cummulantsVLSL architectures

Mathematics Subject Classification ID

Modes of computation (nondeterministic, parallel, interactive, probabilistic, etc.) (68Q10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cited In (5)

• A new approach for the design of linear systolic arrays for computing third-order cumulants
• A systematic design of a parallel program for Dirichlet convolution
• Parametric supplements to systems factorial analysis: identifying interactive parallel processing using systems of accumulators
• Implementation aspects of various higher-order statistics estimators
• Efficient Computation of Higher-Order Cumulant Tensors

Uses Software

• DG2VHDL

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