Integrating side channel security in the FPGA hardware design flow

DOI10.1007/978-3-030-68773-1_13OpenAlexW3127222271MaRDI QIDQ2106708FDOQ2106708

Authors: Alessandro Barenghi, Matteo Brevi, William Fornaciari, Gerardo Pelosi, Davide Zoni 

Publication date: 16 December 2022

Full work available at URL: https://doi.org/10.1007/978-3-030-68773-1_13

zbMATH Keywords

side channel analysisdesign automation and toolsFPGA design flow

Mathematics Subject Classification ID

Cryptography (94A60) Computer science (68-XX)

Cites Work

• GitHub
• Mutual information analysis: a comprehensive study
• Trace-based schedulability analysis to enhance passive side-channel attack resilience of embedded software
• A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
• Title not available (Why is that?)

Cited In (2)

• Generic Side-Channel Countermeasures for Reconfigurable Devices
• Using Virtual Secure Circuit to Protect Embedded Software from Side-Channel Attacks

Uses Software

• Yosys
• GitHub
• SymbiFlow

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