Integrating side channel security in the FPGA hardware design flow

DOI10.1007/978-3-030-68773-1_13MaRDI QIDQ2106708zbMATH OpenOpenAlexFDO

Authors Alessandro Barenghi, Matteo Brevi, William Fornaciari, Gerardo Pelosi, Davide Zoni

Publication date 16 December 2022

Full work available at URL https://doi.org/10.1007/978-3-030-68773-1_13

zbMATH Keywords

design automation and toolsFPGA design flowside channel analysis

Mathematics Subject Classification ID

Computer science (68-XX) Cryptography (94A60)

Cites work

• A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
• GitHub
• scientific article; zbMATH DE number 1759354 (Why is no real title available?)
• Mutual information analysis: a comprehensive study
• Trace-based schedulability analysis to enhance passive side-channel attack resilience of embedded software

Cited in

(2)

• Generic Side-Channel Countermeasures for Reconfigurable Devices
• Using Virtual Secure Circuit to Protect Embedded Software from Side-Channel Attacks

Describes a project that uses

Uses Software

• Yosys
• SymbiFlow
• GitHub

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