Trace-based schedulability analysis to enhance passive side-channel attack resilience of embedded software

DOI10.1016/J.IPL.2014.09.030zbMATH Open1302.68085OpenAlexW2053919488WikidataQ57717460 ScholiaQ57717460MaRDI QIDQ477664FDOQ477664

Authors: Giovanni Agosta, Alessandro Barenghi, Gerardo Pelosi, Michele Scandale 

Publication date: 9 December 2014

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.ipl.2014.09.030

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zbMATH Keywords

cryptographycompilersembedded systems securityside-channel attackstrace theory

Mathematics Subject Classification ID

Cryptography (94A60) Mathematical aspects of software engineering (specification, verification, metrics, requirements, etc.) (68N30)

Cites Work

• Title not available (Why is that?)
• Power Analysis Attacks
• Analysis and Improvement of the Random Delay Countermeasure of CHES 2009
• An Efficient Method for Random Delay Generation in Embedded Software

Cited In (5)

• Custom instruction support for modular defense against side-channel and fault attacks
• Integrating side channel security in the FPGA hardware design flow
• Information Security and Cryptology - ICISC 2005
• An Efficient Method for Random Delay Generation in Embedded Software
• The schedulability of AES as a countermeasure against side channel attacks

Uses Software

• LLVM

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