Memory-efficient high-speed implementation of Kyber on Cortex-M4

DOI10.1007/978-3-030-23696-0_11MaRDI QIDQ2177629zbMATH OpenOpenAlexFDO

Authors Leon Botros, Matthias J. Kannwischer, Peter Schwabe

Publication date 6 May 2020

Full work available at URL https://doi.org/10.1007/978-3-030-23696-0_11

zbMATH Keywords

lattice-based cryptographyARM Cortex-M4number-theoretic transformKyber

Mathematics Subject Classification ID

Cryptography (94A60)

Recommendations

• Faster multiplication in \(\mathbb{Z}_{2^m}[x]\) on Cortex-M4 to speed up NIST PQC candidates
• SIKE round 2 speed record on ARM Cortex-M4
• High-speed key encapsulation from NTRU
• Saber: module-LWR based key exchange, CPA-secure encryption and CCA-secure KEM
• Higher-order masked Saber

Cited in

(13)

• Curve448 on 32-bit ARM Cortex-M4
• Fast NEON-based multiplication for lattice-based NIST post-quantum cryptography finalists
• Verifying post-quantum signatures in 8 kB of RAM
• Dilithium for memory constrained devices
• SIKE round 2 speed record on ARM Cortex-M4
• Full Post-Quantum datagram TLS handshake in the Internet of Things
• A monolithic hardware implementation of Kyber: comparing apples to apples in PQC candidates
• Fast Falcon signature generation and verification using ARMv8 NEON instructions
• Kyber
• Implementing lattice-based PQC on resource-constrained processors: a case study for Kyber/Saber's polynomial multiplication on ARM Cortex-M0/M0+
• Fast first-order masked NTTRU
• Evaluating the potential for hardware acceleration of four NTRU-based key encapsulation mechanisms using software/hardware codesign
• Formal verification of arithmetic masking in hardware and software

Describes a project that uses

Uses Software

• XKCP
• PQM4
• NTRUEncrypt

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