Efficient controller synthesis for a fragment of MTL₀,
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Publication:2249659
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Cites work
- scientific article; zbMATH DE number 4124989 (Why is no real title available?)
- scientific article; zbMATH DE number 1759436 (Why is no real title available?)
- scientific article; zbMATH DE number 3189696 (Why is no real title available?)
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- On Synthesizing Controllers from Bounded-Response Properties
- On the synthesis of discrete controllers for timed systems
- Realizability of real-time logics
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- Safraless Procedures for Timed Specifications
- Solving Sequential Conditions by Finite-State Strategies
- Supervisory Control of a Class of Discrete Event Processes
- Synthesis of Communicating Processes from Temporal Logic Specifications
- Synthesis of Reactive(1) designs
- The benefits of relaxing punctuality
- Using branching time temporal logic to synthesize synchronization skeletons
- Verification, Model Checking, and Abstract Interpretation
Cited in
(7)- Controller Synthesis for MTL Specifications
- Controller Synthesis for MDPs and Frequency LTL $$_{\setminus \mathbf{G}\mathbf U}$$
- Further reduction of minimal first-met bad markings for the computationally efficient synthesis of a maximally permissive controller
- Divergent stutter bisimulation abstraction for controller synthesis with linear temporal logic specifications
- A method for the synthesis of controllers to handle safety, liveness, and real-time constraints
- Real-time policy enforcement with metric first-order temporal logic
- Taming large bounds in synthesis from bounded-liveness specifications
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