Dominant Trio of Poles Assignment in Delayed PID Control Loop
From MaRDI portal
Publication:2863183
DOI10.1007/978-3-319-01695-5_5zbMath1276.93042OpenAlexW37003280MaRDI QIDQ2863183
Jaromír Fišer, Tomáš Vyhlídal, Pavel Zítek
Publication date: 21 November 2013
Published in: Delay Systems (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-319-01695-5_5
pole assignmentabsolute error integralPID controllers tuningquality of the disturbance rejection response
Linear systems in control theory (93C05) Pole and zero placement problems (93B55) Control/observation systems governed by ordinary differential equations (93C15)
Related Items (2)
A universal map of three-dominant-pole assignment for PID controller tuning ⋮ Dynamic similarity approach to control system design: delayed PID control loop
Cites Work
This page was built for publication: Dominant Trio of Poles Assignment in Delayed PID Control Loop