VLSI layouts of complete graphs and star graphs

DOI10.1016/S0020-0190(98)00133-1zbMATHOpenAlexMaRDI QIDQ293402FDO

Authors Chi-Hsiang Yeh, Behrooz Parhami

Publication date 9 June 2016

Published in Information Processing Letters (Search for Journal in Brave)

Full work available at URL http://www.sciencedirect.com/science/article/pii/S0020019098001331?np=y

zbMATH Keywords

parallel processingstar graphscomplete graphsVLSI layout

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10)

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Cites work

• scientific article; zbMATH DE number 3900683 (Why is no real title available?)
• scientific article; zbMATH DE number 52113 (Why is no real title available?)
• A class of recursive interconnection networks: architectural characteristics and hardware cost
• On VLSI layouts of the star graph and related networks
• On the genus of star graphs
• Transposition networks as a class of fault-tolerant robust networks

Cited in

(9)

• An area-maximum edge length trade-off for VSLI layout
• Minimum-diameter cyclic arrangements in mapping data-flow graphs onto VLSI arrays
• A framework for solving VLSI graph layout problems
• On the problem of determining which \((n, k)\)-star graphs are Cayley graphs
• On VLSI layouts of the star graph and related networks
• scientific article; zbMATH DE number 88981 (Why is no real title available?)
• Single-row transformation of complete graphs
• scientific article; zbMATH DE number 2230273 (Why is no real title available?)
• Two models of two-dimensional bandwidth problems

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