An optimised dynamic bottleneck dispatching policy for semiconductor wafer fabrication
DOI10.1080/00207540701805638zbMATH Open1198.90287OpenAlexW2077122862MaRDI QIDQ3055433FDOQ3055433
Authors: Huai Zhang, Zhibin Jiang, Chengtao Guo
Publication date: 7 November 2010
Published in: International Journal of Production Research (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1080/00207540701805638
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Cites Work
Cited In (11)
- Semiconductor lot allocation using robust optimization
- Job order releasing and throughput planning for multi-priority orders in wafer fabs
- Modelling and analysis of wafer fabrication scheduling via generalized stochastic Petri net and simulated annealing
- A dynamic WIP control strategy for bottlenecks in a wafer fabrication system
- A rework-based dispatching algorithm for module process in TFT-LCD manufacture
- Comparison and evaluation of lot-to-order matching policies for a semiconductor assembly and test facility
- Simulation study of a bottleneck-based dispatching policy for a maintenance workforce
- Simulation analysis of dispatching rules for an automated interbay material handling system in wafer fab
- Allocation of Chips to Wafers in a Production Problem of Semiconductor Kits
- Rule-based scheduling in wafer fabrication with due date-based objectives
- Dynamic state-dependent dispatching for wafer fabrication
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