Comparison and evaluation of lot-to-order matching policies for a semiconductor assembly and test facility
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Publication:4497252
DOI10.1080/002075400188627zbMATH Open0944.90554OpenAlexW2170909621MaRDI QIDQ4497252FDOQ4497252
Authors: John Fowler, Kraig R. Knutson, W. Matthew Carlyle 
Publication date: 22 August 2000
Published in: International Journal of Production Research (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1080/002075400188627
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Cited In (6)
- Semiconductor lot allocation using robust optimization
- Forming and scheduling jobs with capacitated containers in semiconductor manufacturing: Single machine problem
- Lot-order assignment applying priority rules for the single-machine total tardiness scheduling with nonnegative time-dependent processing times
- Evaluation of heuristics for a class-constrained lot-to-order matching problem in semiconductor manufacturing
- Heuristic approaches for master planning in semiconductor manufacturing
- Bin covering algorithms in the second stage of the lot to order matching problem
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