Lot-order assignment applying priority rules for the single-machine total tardiness scheduling with nonnegative time-dependent processing times

DOI10.1155/2015/434653MaRDI QIDQ1665667zbMATH OpenOpenAlexWikidataFDO

Authors Jae-Gon Kim, Seung-Kil Lim, June-Young Bang

Publication date 27 August 2018

Published in Mathematical Problems in Engineering (Search for Journal in Brave)

Copyright license Creative Commons Attribution 3.0 Unported

Full work available at URL https://doi.org/10.1155/2015/434653

Mathematics Subject Classification ID

Deterministic scheduling theory in operations research (90B35)

Review text

Summary: Lot-order assignment is to assign items in lots being processed to orders to fulfill the orders. It is usually performed periodically for meeting the due dates of orders especially in a manufacturing industry with a long production cycle time such as the semiconductor manufacturing industry. In this paper, we consider the lot-order assignment problem (LOAP) with the objective of minimizing the total tardiness of the orders with distinct due dates. We show that we can solve the LOAP optimally by finding an optimal sequence for the single-machine total tardiness scheduling problem with nonnegative time-dependent processing times (SMTTSP-NNTDPT). Also, we address how the priority rules for the SMTTSP can be modified to those for the SMTTSP-NNTDPT to solve the LOAP. In computational experiments, we discuss the performances of the suggested priority rules and show the result of the proposed approach outperforms that of the commercial optimization software package.

Recommendations

• Lot scheduling on a single machine to minimize the (weighted) number of tardy orders
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• Optimal Assignment of Total-work-content Due-dates and Sequencing in a Single-machine Shop
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Cites work

• A backward approach in list scheduling algorithms for multi-machine tardiness problems
• A concise survey of scheduling with time-dependent processing times
• A survey of scheduling problems with setup times or costs
• Bin covering algorithms in the second stage of the lot to order matching problem
• Comparison and evaluation of lot-to-order matching policies for a semiconductor assembly and test facility
• Evaluation of heuristics for a class-constrained lot-to-order matching problem in semiconductor manufacturing
• One-Machine Sequencing to Minimize Certain Functions of Job Tardiness
• Scheduling semiconductor multihead testers using metaheuristic techniques embedded with lot-specific and configuration-specific information
• Semiconductor lot allocation using robust optimization
• Some scheduling problems with general position-dependent and time-dependent learning effects
• Some scheduling problems with sum-of-processing-times-based and job-position-based learning effects
• Some single-machine scheduling problems with general effects of learning and deterioration
• The single-machine total tardiness scheduling problem: review and extensions
• Using dispatching rules for job shop scheduling with due date-based objectives

Cited in

(2)

• Impact of priority sequencing decisions on on-time probability and expected tardiness of orders in make-to-order production systems with external due-dates
• Lot scheduling on a single machine to minimize the (weighted) number of tardy orders

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