Low-delay parallel architecture for fractal image compression

DOI10.1007/S00034-015-0088-3zbMATH Open1429.94020OpenAlexW641782711MaRDI QIDQ308069FDOQ308069

Authors: Mamata Panigrahy, Indrajit Chakrabarti, A. S. Dhar 

Publication date: 5 September 2016

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00034-015-0088-3

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zbMATH Keywords

FPGAfractal image compressionisometric transformationparallel architectureSAD

Mathematics Subject Classification ID

Image processing (compression, reconstruction, etc.) in information and communication theory (94A08)

Cites Work

• Image compression: A study of the iterated transform method
• Fast fractal image compression using spatial correlation
• Iterated function systems and the global construction of fractals
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• A JPEG chip for image compression and decompression
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• An FPGA-based design for an image compressor
• Parallel, pipelined and folded architectures for computation of 1-D and 2-D DCT in image and video codec

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