A high performance EBCOT coding and its VLSI architecture
From MaRDI portal
Publication:5490402
zbMATH Open1099.68631MaRDI QIDQ5490402FDOQ5490402
Authors:
Publication date: 4 October 2006
Recommendations
- High-speed and low-power IP for embedded block coding with optimized truncation (EBCOT) sub-block in JPEG2000 system implementation
- High performance word level sequential and parallel coding methods and architectures for bit plane coding
- VLSI architectures of the 1-D and 2-D discrete wavelet transforms for JPEG 2000
- scientific article; zbMATH DE number 1941103
- Low-delay parallel architecture for fractal image compression
embedded block coding with optimized truncationEBCOTbit plane-parallel and pass-parallelblock encoder
Cited In (6)
- High-speed and low-power IP for embedded block coding with optimized truncation (EBCOT) sub-block in JPEG2000 system implementation
- Improved algorithm for RDO in JPEG2000 encoder and its IC design
- CAVLC coding algorithm and FPGA realization of high-speed entropy encoder
- High speed 4-symbol arithmetic encoder architecture for embedded zero tree-based compression
- Title not available (Why is that?)
- High performance word level sequential and parallel coding methods and architectures for bit plane coding
This page was built for publication: A high performance EBCOT coding and its VLSI architecture
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5490402)