Memory arbiter synthesis and verification for a radar memory interface card

zbMATH Open1087.68520MaRDI QIDQ3370733FDOQ3370733

Authors: Juhan Ernits 

Publication date: 8 February 2006

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zbMATH Keywords

formal analysisguided model checkingbit-state hashing

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Reliability, testing and fault tolerance of networks and computer systems (68M15) Specification and verification (program logics, model checking, etc.) (68Q60)

Cited In (1)

• Model-based verification, optimization, synthesis and performance evaluation of real-time systems

Uses Software

• Uppaal2k
• Uppaal
• UPPAAL CORA

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