swMATH1595MaRDI QIDQ14301FDOQ14301
Author name not available (Why is that?)
Official website: http://www.it.uu.se/research/group/darts/uppaal/about.shtml
Cited In (51)
- Schedulability of asynchronous real-time concurrent objects
- Compositional schedulability analysis of real-time actor-based systems
- But what if I don't want to wait forever?
- False loop detection in the IEEE 1394 tree identify phase
- IEEE 1394 tree identify protocol: Introduction to the case study
- Memory arbiter synthesis and verification for a radar memory interface card
- Automated Technology for Verification and Analysis
- Computer Aided Verification
- Advances in verification of time Petri nets and timed automata. A temporal logic approach.
- Verifying distributed real-time properties of embedded systems via graph transformations and model checking
- Linear parametric model checking of timed automata
- Title not available (Why is that?)
- TCTL inevitability analysis of dense-time systems
- SAT-based unbounded model checking of timed automata
- Probabilistic model checking of deadline properties in the IEEE 1394 fireWire root contention protocol
- Modeling and verification of hybrid dynamic systems using multisingular hybrid Petri nets
- Performance analysis of probabilistic timed automata using digital clocks
- Analyzing real-time systems: Theory and tools
- Almost ASAP semantics: from timed models to timed implementations
- Verifying the IEEE 1394 fireWire tree identify protocol with SMV
- When are timed automata weakly timed bisimilar to time Petri nets?
- Title not available (Why is that?)
- Kronos
- Rabbit
- TAXYS
- TREX
- DiVer
- VerICS
- E-LOTOS
- MOTOR
- SHARPE
- HyTech
- Uppaal
- Design and Verification of Fault-Tolerant Components
- Sumatra
- Viptos
- AN INVERSE METHOD FOR PARAMETRIC TIMED AUTOMATA
- UPPAAL CORA
- Fun with fireWire: A comparative study of formal verification methods applied to the IEEE 1394 root contention protocol
- Runtime monitoring of contract regulated web services
- Slicing of timed automata with discrete data
- Correct Hardware Design and Verification Methods
- Analysis of scheduling behaviour using generic timed automata
- Symbolic model checking for probabilistic timed automata
- Numerical coverage estimation for the symbolic simulation of real-time systems
- A tool for the syntactic detection of Zeno-timelocks in timed automata
- Title not available (Why is that?)
- Title not available (Why is that?)
- A timed verification of the IEEE 1394 Leader election protocol
- A survey of formal methods applied to leader election in IEEE 1394
- Modelling and analysis of hybrid supervisory systems. A Petri net approach.
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