Complete test generation method for all stuck-at faults in combinational circuits

DOI10.1080/00207219008921209MaRDI QIDQ3479983zbMATH OpenOpenAlexFDO

Authors Hasan Guran, Ugur Halici

Publication date 1990

Published in International Journal of Electronics (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1080/00207219008921209

zbMATH Keywords

logic gatescombinational logic circuitscomplete fault detection test setsstuck- at faults

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

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