Complete test generation method for all stuck-at faults in combinational circuits

DOI10.1080/00207219008921209zbMATH Open0701.94020OpenAlexW1975256610MaRDI QIDQ3479983FDOQ3479983

Authors: Hasan Guran, Ugur Halici 

Publication date: 1990

Published in: International Journal of Electronics (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1080/00207219008921209

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zbMATH Keywords

logic gatescombinational logic circuitscomplete fault detection test setsstuck- at faults

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Cited In (10)

• An algorithm for stuck-at fault coverage analysis of combinational and sequential logic circuits
• Test Sets for Combinational Logic—The Edge-Tracing Approach
• Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults
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• An efficient algorithm for single and multiple fault test sets generation
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• An algorithm to generate complete test sets for stuck-at faults in combinational logic circuits
• Complete test-set generation for bridging faults in combinational-logic circuits

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