Design of test sequences for VLSI self-testing using LFSR

DOI10.1109/18.52485zbMATH Open0704.94013OpenAlexW2149459130MaRDI QIDQ3484763FDOQ3484763

Authors: Henk D. L. Hollmann 

Publication date: 1990

Published in: IEEE Transactions on Information Theory (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/18.52485

Recommendations

• Theoretical properties of LFSRs for built-in self test
• Specified sequence linear feedback shift registers
• Design of universal test sequences for VLSI
• Generation of test patterns and data compression using nonlinear shift registers
• Publication:3470412

zbMATH Keywords

maximum lengthlinear feedback shift registerVLSI self-testing

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Communication, information (94A99)

Cited In (6)

• Zero-aliasing for modeled faults
• Test-set partitioning for multi-weighted random LFSRs
• Design of universal test sequences for VLSI
• Proof of a conjecture and a bound on the imbalance properties of LFSR subsequences
• The estimates of trigonometric sums and new bounds on a mean value, a sequence and a cryptographic function
• Title not available (Why is that?)

This page was built for publication: Design of test sequences for VLSI self-testing using LFSR

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3484763)