Zero-aliasing for modeled faults

DOI10.1109/12.475124zbMATH Open1054.68521OpenAlexW2138141123MaRDI QIDQ4421145FDOQ4421145

Authors: Mody Lempel, Sandeep K. Gupta 

Publication date: 1995

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://semanticscholar.org/paper/3d913908a81c1e76a456263ddc362652caede4e1

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zbMATH Keywords

VLSI circuitssignature analysisBuilt-In Self-Test

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cited In (6)

• Counter-based compaction: Delay and stuck-open faults
• Aliasing error for a mask ROM built-in self-test
• On the maximum value of aliasing probabilities for single input signature registers
• Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers
• Title not available (Why is that?)
• Aliasing errors in parallel signature analyzers

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