Algorithm and circuit design for secondary Booth encoded multiplier

zbMATH Open1150.94326MaRDI QIDQ3500764FDOQ3500764

Authors: Xiao-Dong Yan, S. G. Li 

Publication date: 3 June 2008

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zbMATH Keywords

multipliermodule multiplicationRivest Shamir and Adleman (RSA) algorithmsecondary Booth recoding

Mathematics Subject Classification ID

Cryptography (94A60)

Cited In (3)

• A design of low latency multiplier/mac unit for public-key cryptography
• A new algorithm for design of the Booth-based multiplier unit
• To Booth or not to Booth

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