A design of low latency multiplier/mac unit for public-key cryptography

zbMATH Open1174.68435MaRDI QIDQ3609537FDOQ3609537

Lina Zhang, Jianhua Chen, Jiahong Zhang

Publication date: 6 March 2009

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zbMATH Keywords

multipliercompressorBooth recoderlook-ahead adder

Mathematics Subject Classification ID

Cryptography (94A60) Coding and information theory (compaction, compression, models of communication, encoding schemes, etc.) (aspects in computer science) (68P30)

Cited In (3)

• A 16-bit by 16-bit MAC design using fast 5:3 compressor cells
• A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach
• Algorithm and circuit design for secondary Booth encoded multiplier

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