Properties and performance bounds for timed marked graphs

DOI10.1109/81.139289MaRDI QIDQ4017665zbMATH OpenOpenAlexFDO

Authors Javier Campos, Giovanni Chiola, J. M. Colom, Manuel Silva

Publication date 16 January 1993

Published in IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/81.139289

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

Cited in

(12)

• Petri nets for the design and operation of manufacturing systems
• Steady-state performance evaluation of continuous mono-T-semiflow Petri nets
• Performance safety enforcement in strongly connected timed event graphs
• Timed Petri nets with reset for pipelined synchronous circuit design
• An upper bound on the cycle time of a stochastic marked graph using incomplete information on the transition firing time distributions
• Performance safety enforcement in stochastic event graphs against boost and slow attacks
• Cycle time of a P-time event graph with affine-interdependent residence durations
• Timed event graph-based cyclic reconfigurable flow shop modelling and optimization
• Firing rate optimization of cyclic timed event graphs by token allocations
• Design and verification of pipelined circuits with timed Petri nets
• A survey on performance evaluations in time-dependent Petri nets
• Cyclic scheduling for F.M.S.: Modelling and evolutionary solving approach

This page was built for publication: Properties and performance bounds for timed marked graphs

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4017665)