Design and verification of pipelined circuits with timed Petri nets

DOI10.1007/S10626-022-00371-7zbMATH Open1519.93147MaRDI QIDQ6160969FDOQ6160969

Authors: Rémi Parrot, Mikaël Briday, Olivier H. Roux 

Publication date: 26 June 2023

Published in: Discrete Event Dynamic Systems (Search for Journal in Brave)

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zbMATH Keywords

model checkingresource sharingtimed Petri netsynchronous circuitpipeline optimizationtime-multiplexing

Mathematics Subject Classification ID

Discrete event control/observation systems (93C65) Applications of graph theory to circuits and networks (94C15)

Cites Work

• Model-checking in dense real-time
• TCTL model checking of time Petri nets
• Retiming synchronous circuitry
• Properties and performance bounds for timed marked graphs
• Model Checking One-clock Priced Timed Automata
• Universality analysis for one-clock timed automata
• Time and Petri nets
• Title not available (Why is that?)
• Timed Petri nets with reset for pipelined synchronous circuit design

Cited In (2)

• Timed Petri nets with reset for pipelined synchronous circuit design
• Title not available (Why is that?)

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