Design and verification of pipelined circuits with timed Petri nets

DOI10.1007/S10626-022-00371-7zbMATH Open1519.93147MaRDI QIDQ6160969FDOQ6160969

Authors Rémi Parrot, Mikaël Briday, Olivier H. Roux

Publication date 26 June 2023

Published in Discrete Event Dynamic Systems (Search for Journal in Brave)

zbMATH Keywords

model checkingresource sharingtimed Petri netsynchronous circuitpipeline optimizationtime-multiplexing

Mathematics Subject Classification ID

Discrete event control/observation systems (93C65) Applications of graph theory to circuits and networks (94C15)

Recommendations

• Timed Petri nets with reset for pipelined synchronous circuit design
• Retiming synchronous circuitry
• Understanding retiming through maximum average-delay cycles
• scientific article; zbMATH DE number 1696445
• Retiming: Theory and practice

Cites work

• scientific article; zbMATH DE number 3651705 (Why is no real title available?)
• Model Checking One-clock Priced Timed Automata
• Model-checking in dense real-time
• Properties and performance bounds for timed marked graphs
• Retiming synchronous circuitry
• TCTL model checking of time Petri nets
• Time and Petri nets
• Timed Petri nets with reset for pipelined synchronous circuit design
• Universality analysis for one-clock timed automata

Cited in

(2)

• Timed Petri nets with reset for pipelined synchronous circuit design
• scientific article; zbMATH DE number 5814792 (Why is no real title available?)

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