Timed Petri nets with reset for pipelined synchronous circuit design
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Publication:2117152
DOI10.1007/978-3-030-76983-3_4zbMATH Open1489.68166OpenAlexW3172377947MaRDI QIDQ2117152FDOQ2117152
Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85) Networks and circuits as models of computation; circuit complexity (68Q06)
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Cites Work
- scientific article; zbMATH DE number 3328724 (Why is no real title available?)
- A theory of timed automata
- Complexity results for 1-safe nets
- Model-checking in dense real-time
- Properties and performance bounds for timed marked graphs
- Retiming synchronous circuitry
- TCTL model checking of time Petri nets
- The expressive power of time Petri nets
- Time and Petri nets
- Universality analysis for one-clock timed automata
Cited In (4)
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