Timed Petri nets with reset for pipelined synchronous circuit design

DOI10.1007/978-3-030-76983-3_4MaRDI QIDQ2117152zbMATH OpenOpenAlexFDO

Authors Rémi Parrot, Mikaël Briday, Olivier H. Roux

Publication date 21 March 2022

Full work available at URL https://doi.org/10.1007/978-3-030-76983-3_4

Mathematics Subject Classification ID

Networks and circuits as models of computation; circuit complexity (68Q06) Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

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Cites work

• A theory of timed automata
• Complexity results for 1-safe nets
• scientific article; zbMATH DE number 3328724 (Why is no real title available?)
• Model-checking in dense real-time
• Properties and performance bounds for timed marked graphs
• Retiming synchronous circuitry
• TCTL model checking of time Petri nets
• The expressive power of time Petri nets
• Time and Petri nets
• Universality analysis for one-clock timed automata

Cited in

(4)

• Waiting nets
• Modular synthesis of timed circuits using partial orders on LPNs
• Design and verification of pipelined circuits with timed Petri nets
• Waiting Nets: State Classes and Taxonomy

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