Timed Petri nets with reset for pipelined synchronous circuit design
DOI10.1007/978-3-030-76983-3_4zbMATH Open1489.68166OpenAlexW3172377947MaRDI QIDQ2117152FDOQ2117152
Authors: Rémi Parrot, Mikaël Briday, Olivier H. Roux 
Publication date: 21 March 2022
Full work available at URL: https://doi.org/10.1007/978-3-030-76983-3_4
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Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85) Networks and circuits as models of computation; circuit complexity (68Q06)
Cites Work
- A theory of timed automata
- Model-checking in dense real-time
- The expressive power of time Petri nets
- TCTL model checking of time Petri nets
- Retiming synchronous circuitry
- Properties and performance bounds for timed marked graphs
- Universality analysis for one-clock timed automata
- Title not available (Why is that?)
- Complexity results for 1-safe nets
- Time and Petri nets
Cited In (4)
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