New low-power tristate circuits in positive feedback source-coupled logic

DOI10.1155/2011/670508zbMATH Open1237.94160OpenAlexW2125362101WikidataQ58690677 ScholiaQ58690677MaRDI QIDQ415808FDOQ415808

Neeta Pandey, Jaya Chaudhary, Maneesha Gupta, Ranjana Sridhar, Kirti Gupta

Publication date: 9 May 2012

Published in: Journal of Electrical and Computer Engineering (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1155/2011/670508

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Mathematics Subject Classification ID

Applications of design theory to circuits and networks (94C30)

Cites Work

• Modeling and Evaluation of Positive-Feedback Source-Coupled Logic

Cited In (2)

• Two-phase clocked CMOS adiabatic logic
• Power-delay optimization of D-latch/MUX source coupled logic gates

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