Algorithm and Hardware for a Merge Sort Using Multiple Processors
From MaRDI portal
Publication:4160424
DOI10.1147/rd.225.0509zbMath0382.68057OpenAlexW2074747378WikidataQ113758531 ScholiaQ113758531MaRDI QIDQ4160424
No author found.
Publication date: 1978
Published in: IBM Journal of Research and Development (Search for Journal in Brave)
Full work available at URL: https://semanticscholar.org/paper/68b9870d962ecae4f132797dffda6b69353cb216
Related Items (6)
A VLSI algorithm for sorting variable-length character strings ⋮ A parallel sorting scheme whose basic operation sortsN elements ⋮ Optimal parallel algorithms for computing convex hulls and for sorting ⋮ VLSI-sorting evaluated under the linear model ⋮ Linear sorting with O(log n) processors ⋮ A new parallel sorting algorithm based upon min-mid-max operations
This page was built for publication: Algorithm and Hardware for a Merge Sort Using Multiple Processors